DR8051 Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – 8-bit RISC Microcontroller ver 2.00

PIN TYPE
DESCRIPTION
clk
input Global clock
rst
input Global reset
port0i[7:0]
input Port 0 input
port1i[7:0]
input Port 1 input
port2i[7:0]
input Port 2 input
port3i[7:0]
input Port 3 input
prgdata[7:0]
input Data bus from program memory
xramdatai[7:0] input Data bus from ext. data memory
ramdati[7:0]
input Data bus from int. data memory
sfrdatai[7:0]
input Data bus from user SFR’s
int0
input External interrupt 0
int1
input External interrupt 1
t0
input Timer 0 input
t1
input Timer 1 input
gate0
input Timer 0 gate input
gate1
input Timer 1 gate input
rxdi
input Serial receiver input
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
port3o[7:0]
output Port 3 output
prgaddr[15:0] output Program memory address bus
xramaddr[23:0] output External data memory address bus
xramdatao[7:0] output Data bus for external data memory
xramwr
output External data memory write
xramrd
output External data memory read
ramsfraddr[7:0] output RAM and SFR’s address bus
ramsfrdatao[7:0] output Data bus for internal data memory
ramwe
output Internal data memory write enable
ramrd
output Internal data memory read
sfrwe
output User SFR’s write enable
sfrrd
output User SFR’s read
rxdo
output Serial receiver output
txd
output Serial transmitter output
The following table gives a survey about
the DR8051 performance in ALTERA®
devices after Place & Route (all key fea-
tures have been included):
a) FLEX™ 10K100E-1
Area
- 2049 LC + 1EAB
System clock f_max - 58 MHz
b) APEX™ 20K100E-1
Area
- 2120 LC
System clock f_max - 58 MHz
c) ACEX™ 1K100-1
Area
- 2096 LC + 1 EAB
System clock f_max - 57 MHz
PERFORMANCE
MODIFICATIONS
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