DR8051 Datasheet, PDF (2/4 Pages) List of Unclassifed Manufacturers – 8-bit RISC Microcontroller ver 2.00

ü FUCOM - compare
ü FCHS - change sign
ü FABS - absolute value
♦ Floating-Point math coprocessor - IEEE-
754 standard single precision real, word
and short integers
ü FADD, FSUB- addition, subtraction
ü FMUL, FDIV- multiplication, division
ü FSQRT- square root
ü FUCOM- compare
ü FCHS - change sign
ü FABS - absolute value
ü FSIN, FCOS- sine, cosine
ü FPTAN, FPATAN- tangent, arcs tan-
gent
DELIVERABLES
♦ VHDL, Verilog source code
♦ VITAL simulation model
♦ HDL test bench
♦ Synthesis scripts
♦ Technical documentation
♦ Technical support
Up to 104 External Special Function
Registers (ESFRs) may be added to the
DR8051 design. ESFRs are memory
mapped into Direct Memory between
addresses 80 hex and FF hex in the
same manner as core SFRs and may
occupy any address that is not occupied
by a core SFR.
ü STRETCH MEMORY CYCLE REGISTER:
Allows applications software to adjust
to different external RAM speeds
(XRAMWR and XRAMRD pulse be-
tween 1 – 8 clock cycles).
ü EXTERNAL RAM:
Allows applications software to access
up to 16 MB of external data memory.
Extra DPP( Data Page Pointer) register
is used for segments swapping.
SYMBOL
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
prgdata(7:0) prgaddr(15:0)
xramdatai(7:0) xramdatao(7:0)
xramaddr(23:0)
xramrd
xramwr
DESIGN FEATURES
ü DATA MEMORY:
The DR8051 can address Internal
Data Memory of up to 256 bytes, and up
to 16M bytes of external Data RAM via
the function interconnect signals. The
Internal Data Memory can be imple-
mented as Single-Port synchronous or
asynchronous RAM.
ramdatai(7:0) ramsfrdatao(7:0)
sfrdatai(7:0) ramsfraddr(7:0)
int0
int1
t0
gate0
t1
gate1
rxdi
rst
clk
ramrd
ramwe
sfrrd
sfrwe
rxdo
txd
ü EXTERNAL SPECIAL FUNCTION REGIS-
TERS:
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