LM3S612 Datasheet, PDF (295/419 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S612 Data Sheet
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the
corresponding mask.
SSI Interrupt Mask (SSIIM)
Offset 0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXIM RXIM RTIM RORIM
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
TXIM
2
RXIM
1
RTIM
0
RORIM
Type
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI Transmit FIFO Interrupt Mask
0: TX FIFO half-full or less condition interrupt is masked.
1: TX FIFO half-full or less condition interrupt is not masked.
SSI Receive FIFO Interrupt Mask
0: RX FIFO half-full or more condition interrupt is masked.
1: RX FIFO half-full or more condition interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
0: RX FIFO time-out interrupt is masked.
1: RX FIFO time-out interrupt is not masked.
SSI Receive Overrun Interrupt Mask
0: RX FIFO overrun interrupt is masked.
1: RX FIFO overrun interrupt is not masked.
April 27, 2007
295
Preliminary