LM3S612 Datasheet, PDF (174/419 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Offset 0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
RO
Reset
0
reserved
RO
RO
RO
0
0
0
CBERIS CBMRIS TBTORIS
RO
RO
RO
RO
RO
0
0
0
0
0
reserved
RO
RO
0
0
RTCRIS CAERIS CAMRIS TATORIS
RO
RO
RO
RO
RO
0
0
0
0
0
Bit/Field
31:11
10
9
8
7:4
3
2
1
0
Name
reserved
CBERIS
CBMRIS
TBTORIS
reserved
RTCRIS
CAERIS
CAMRIS
TATORIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
Reserved bits return an indeterminate value, and should never
be changed.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
174
April 27, 2007
Preliminary