QL8025 Datasheet, PDF (26/49 Pages) List of Unclassifed Manufacturers – LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

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t_SWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
t_HWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
t_SWD
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
t_HWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
t_SWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active
edge of the WRITE CLOCK
t_HWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
t_WCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
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0.675 ns
-
0 ns
-
0.654 ns
-
0 ns
-
0.623 ns
-
0 ns
-
-
4.38 ns
WCLK
WA
tSWA
tHWA
WD
tSWD
tHWD
WE
tSWE
tHWE
RD
old data
new data
tWCRD
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