QL8025 Datasheet, PDF (1/49 Pages) List of Unclassifed Manufacturers – LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

(FOLSVH,, )DPLO\ 'DWD 6KHHW
‡ ‡ ‡ ‡ ‡ ‡ _{/RZ 3RZHU )3*$ &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0}
'HYLFH +LJKOLJKWV
)OH[LEOH 3URJUDPPDEOH /RJLF
‡ 0.18 µ, six layer metal CMOS process
‡ 1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O
‡ Up to 4,008 dedicated flip-flops
‡ Up to 55.3 K embedded RAM Bits
‡ Up to 313 I/O
‡ Up to 370 K system gates
‡ IEEE 1149.1 Boundary Scan Testing
Compliant
‡ Low Power Capability
(PEHGGHG 'XDO 3RUW 65$0
‡ Up to twenty-four 2,304 bit Dual Port High
Performance SRAM Blocks
‡ Up to 55,296 embedded RAM bits
‡ RAM/ROM/FIFO Wizard for automatic
configuration
‡ Configurable and cascadable
3URJUDPPDEOH ,2
‡ High performance I/O cell with Tco< 3 ns
‡ Programmable Slew Rate Control
‡ Programmable I/O Standards:
‡ LVTTL, LVCMOS, LVCMOS18, PCI,
GTL+, SSTL2, and SSTL3
‡ Independent I/O Banks capable of
supporting multiple standards in one device
‡ I/O Register Configurations: Input,
Output, Output Enable (OE)
$GYDQFHG &ORFN 1HWZRUN
‡ Multiple dedicated Low Skew Clock
Networks
‡ High drive input-only networks
‡ Quadrant-based segmentable clock networks
‡ User Programmable Phase Locked Loops
(PEHGGHG &RPSXWDWLRQDO 8QLWV
(&8V
Hardwired DSP building blocks with integrated
Multiply, Add, and Accumulate Functions.
6HFXULW\ )HDWXUHV
The QuickLogic products come with secure
ViaLink technology that protects intellectual
property from design theft and reverse
engineering. No external configuration memory
needed; Instant-on at Power-up.
PLL
Embedded RAM Blocks
PLL
Embeded Computational Units
Fabric
PLL
Embedded RAM Blocks
PLL
)LJXUH  (FOLSVH,, %ORFN 'LDJUDP
‹  4XLFN/RJLF &RUSRUDWLRQ
Preliminary
ZZZTXLFNORJLFFRP ^{‡‡‡‡‡‡}