WT62P1 Datasheet, PDF (23/48 Pages) List of Unclassifed Manufacturers – microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface

WT62P1
Data Sheet Rev. 1.01
Master/Slave I²C interface
The master/slave I²C interface is provided for communicating with other I²C devices in the monitor such
as EEPROM, OSD, deflection IC and so on.
Master Mode
To choose master mode, clear the SLAVE bit. The clock frequency can be programmed to 50KHz,
100kHz, 200kHz or 400KHz by setting MCLK1 and MCLK2 bits.
Send out START and the first byte (START, 7-bit address and R/W bit)
First, clear I2CRW bit to select transmitter mode and write first byte (7-bit address and R/W bit) to
MI2C_TX register. Then set MSTR bit, master will generate a START condition and send out the first
byte with the clock speed specified in MCLK1 and MCLK2 bits. After the whole data byte is transmitted
and the 9th bit is received, the MI2CRDY bit is set and generates an interrupt if it is enabled. The 9th bit
will be stored in RXNAK2 bit for checking the slave acknowledge or not. The SCL2 pin will keep low to
wait next byte operation.
Send out the following bytes
If it is a write command, write a data byte to MI2C_TX register, then write any value to I2C_AR register to
clear MI2CRDY bit. It will send out the data byte and store the acknowledge bit from slave in RXACK2 bit.
Again, the MI2CRDY bit is set after the acknowledge bit is received.
If it is a read command, set I2CRW bit to be receiver mode and write TXACK2 bit to determine what will
be sent on acknowledge bit, then write MI2C_AR register to clear I2CRDY bit and it will send out the
clock for receiving next byte. After the acknowledge bit is transmitted, the I2CRDY bit will be set. If
master wants to stop the read operation, send NACK on acknowledge bit to inform slave device.
Send out STOP
Set MSTOP bit will generate STOP condition.
Slave Mode
The slave mode operation is same as DDC interface in DDC2 state. First, set the SLAVE bit and set the
I2CRW bit to be receiver mode. When CPU is ready to receive, clear TXNAK2 bit. It will response ACK
when a START condition followed by an address (which is equal to I2C_ADR register) are received. An
interrupt can be generated if it is enabled and the R/W bit is stored in SRW bit for checking read/write
operation. After the ACK bit, SCL2 pin outputs low level to stop the clock for handshaking.
If a write command is received (SRW bit=0), read the I2C_RX register, clear I2CRW bit to receive next
byte, then write I2C_ADR to clear I2CRDY bit and stop pulling low the SCL2 pin for receiving next byte
from master. The output acknowledge bit is controlled by TX NAK2 bit.
If a read command is received (SRW bit=1), write data to I2C_TX register, clear I2CRW bit and write
I2C_ADR register to clear I2CRDY bit and stop pulling low the SCL2 pin for master sending out clock
The received acknowledge bit is stored in RXNAK2 bit.
Weltrend Semiconductor, Inc.
Page 24