SI5600 Datasheet, PDF (22/28 Pages) List of Unclassifed Manufacturers – SiPHY-TM OC-192/STM-64 SONET/SDH TRANSCEIVER

Si5600
Pin Number(s)
Name
I/O Signal Level
Description
D12
RXMSBSEL
I
LVTTL
Data Bus Receive Order.
This determines the order of the received data
bits on the output bus.
For RXMSBSEL = 0, the first data bit received is
output on RXDOUT[0] and following data bits are
output on RDOUT[1] through RXDOUT[15].
For RXMSBSEL = 1, the first data bit is output on
RXDOUT[15] and following data bits are output
on RXDOUT[14] through RXDOUT[0].
C11
RXREXT
External Bias Resistor.
This resistor is used by the receiver circuitry to
establish bias currents within the device. This pin
must be connected to GND through a 3.09 kΩ
(1%) resistor.
C9
RXSQLCH
I
LVTTL
Data Squelch.
When this input is low the data on RXDOUT is
forced to 0. Set high for normal operation.
C4
SLICELVL
I
Slicing Level Adjustment.
Applying an analog voltage to this pin allows
adjustment of the slicing level applied to the input
data eye. Tieing this input high nominally sets the
slicing offset to 0.
N1–2
TXCLK16IN+,
I
TXCLK16IN–
LVDS
Differential Data Clock Input.
The rising edge of this input clocks data present
on TXDIN into the device.
P1–2
TXCLK16OUT+,
O
TXCLK16OUT–
LVDS
Divided Down Output Clock.
This clock output is generated by dividing down
the high speed output clock, TXCLKOUT, by a
factor of 16. It is intended for use in counter
clocking schemes that transfer data between the
system ASIC and the Si5600.
K12
TXCLKDSBL
I
LVTTL
High Speed Clock Disable
When this input is high, the output driver for
TXCLKOUT is disabled. In applications that do
not require the output data clock, the output clock
driver should be disabled to save power.
G1, H1
TXCLKOUT+,
O
TXCLKOUT–
CML
High Speed Clock Output.
The high speed output clock, TXCLKOUT, is gen-
erated by the PLL in the clock multiplier unit. Its
frequency is nominally 16 or 64 times the
selected reference source.
22
Preliminary Rev. 0.31