CH5001A Datasheet, PDF (22/34 Pages) List of Unclassifed Manufacturers – CMOS COLOR DIGITAL VIDEO CAMERA

CHRONTEL
Table 9. Operating modes for 24 MHz MCLK
ELFA
M
[2:0]
FR
[2:0]
Total
Lines
Blank
Lines /
Frame
MCLK /
Line
0
1,3
000
467
178
1716
0
1,3
001
583
294
1716
0
1,3
010
700
411
1716
0
1,3
011
933
644
1716
0
1,3
100
1166
877
1716
0
1,3
101
1749
1460
1716
0
1,3
110
3497
3208
1716
0
1,3
111
13987
13698
1716
1
1,3
001
289
3464
1
1,3
010
289
4152
1
1,3
011
289
5536
1
1,3
100
289
6920
1
1,3
101
289
10384
1
1,3
110
289
20760
1
1,3
111
289
83048
CH5001A
Blank
MCLK /
Line
308
308
308
308
308
308
308
308
648
1336
2720
4104
7568
17944
80232
Frame
Rate
(Hz)
30
24
20
15
12
8
4
1
24
20
15
12
8
4
1
Max Shutter
Length
(register value)
99,957
124,839
149,935
199,914
249,892
374,946
749,892
2,097,151
124,704
149,472
199,296
249,120
373,824
747,360
2,097,151
Max
Shutter
Time
(mS)
33
42
50
67
83
125
250
699
42
50
66
83
125
249
699
Bits 7-4 (RNUM#) of the FR register contain the revision number of the CH5001 device. These bits are read only.
When using ELFA=1, if 30 Hz frame rate is desired a 30MHz crystal should be used, and the 24MHz MCLK control
(MCE=0) should be selected. All frame rates will be scaled by the value of 30/24.
Horizontal Start Register
BIT:
7
6
SYMBOL:
TYPE:
DEFAULT:
Symbol: HS
Address:02h
Bits:6
5
4
3
2
1
0
HS5
HS4
HS3
HS2
HS1
HS0
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
1
Register HS determines the number of pixels between the leading edge of H Sync and the first active pixel to be
output on the Y[7:0] and C[7:0] pins. The number is in units of pixels; the range is from 0 to 63 CLKOUT and must
be limited to 38 when ELFA=1. When M[2:0] = 4 or 5, this register is ignored and the timing below is followed
assuming 16-bit output mode. Values are doubled for 8-bit output mode
M[2:0]
Leading
Edge of ->
H Sync
H Delay
Border
Active
Border
(CLKOUT) (CLKOUT) (CLKOUT) (CLKOUT)
Blank
(CLKOUT)
Total
(CLKOUT)
4 - NTSC
5 - PAL
122
8
704
8
132
8
704
8
16
858
12
864
22
201-0000-032 Rev 3.0, 6/2/99