V20W Datasheet, PDF (20/24 Pages) List of Unclassifed Manufacturers – PIEZOELECTRIC ENERGY HARVESTERS

APPLICATIONS INFORMATION - LOAD ISOLATION EXAMPLE
Considerations for Conversion Efficiency
Converter efficiency is defined as the output power
divided by the input power times 100%.
The losses from the circuit’s front-end components
(leakage across the storage capacitor, comparator, and
R1-R3) will be small (uA) and largely proportional to
the C1 voltage setpoint. Minimizing losses here is
straightforward by appropriate component selection of
C1 and suitably large values of R1 – R3. These small
losses will occur for the entire time that voltage is
present on C1.
The remaining controllable losses will occur in the
step-down converter section and, apart from the
LT1474’s shutdown current, occur only during the ON-
time of the output. The main losses will come from
three sources: V_IN current, I²R losses, and catch diode
losses.
V_IN
The V_IN current of the LT1474 is due to two
components: the DC bias current and the gate charge
current of its internal P-channel switch. Both are
proportional to V_IN; however, at load currents > 1mA,
the DC bias current (from 9uA at no load to 100uA in
continuous mode) is negligible compared to the gate
charge losses. Each time the gate is switched on and
off, a packet of charge dQ moves from V_IN to ground.
In continuous mode, I_GATE = fQp where Qp is the gate
charge of the internal switch and f is the switching
frequency. Since V_IN is pre-set according to piezo
efficiency considerations, the best way to minimize this
loss is to keep the output duty cycle low.
Resistive (I²R) Losses
The resistances in the current path (The ON-resistance
of the internal switch, current sense resistor, and
inductor) contribute resistive losses. At low values of
V_IN, switch losses will dominate, and can be minimized
by using a suitably large inductor and low I_PEAK. At
higher supply voltages, these losses are proportional to
load.
Catch Diode Losses
The catch diode, D7, introduces a loss (V*I) as it
conducts during the switch off-time, proportional to its
forward voltage, and more pronounced at high supply
voltage where the switch on-time is shorter. Again, V_IN
is fixed for piezo efficiency reasons, so this loss is best
minimized by minimizing the diode V_f and converter
duty cycle. By lowering the duty cycle, a reduction in V_f
of the catch diode will improve efficiency even though
low-V_f diodes tend to have much higher reverse
leakage currents, which will produce loss during the
switch ON-time. In any event, the catch diode must be
sized to safely handle I_PEAK at nearly 100% duty cycle
(worst-case condition; output shorted).
The selection of 100uH inductor should be considered
a minimum, for use in conjunction with high I_PEAK
values. Particularly in applications where space is not
constrained or I_PEAK must be reduced, inductors as
large as 1000uH may be required for maximum
efficiency. The ideal range of inductor size at a given
I_MAX is a trade-off between the increased resistance of
higher-value inductors and the increased switching
rates required for lower-value inductors.
At light loads, the output duty cycle will rise and losses
in the conversion stage (leakage, switching and catch
diode losses) will accrue. This may or may not be a
problem; it could simply mean that more power is
available than the load can use.
REVISION N0. 002 REVISION DATE: 01-23-2013
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