OV8610 Datasheet, PDF (2/28 Pages) List of Unclassifed Manufacturers – Advanced Information Preliminary

Advanced Information
Preliminary
OV8610/OV8110
OV8610 SINGLE-CHIP CMOS VGA COLOR DIGITAL CAMERA
OV8110 SINGLE-CHIP CMOS VGA B&W DIGITAL CAMERA
Pin Description
Table 1. Pin Description
Pin No.
01
02
Name
SVDD
RESET
03
AGCEN
Pin Type
VIN
Function
(Default=0)
Function
(Default=0)
04
FREX
Function
(Default=0)
05
VREQ
06
ASUB
07
AGND
08
AVDD
09
PWDN
VREF (1.5V)
VIN
VIN
VIN
Function
(Default=0)
10
HVDD
11
VCCHG
12
SCCBB
VREF (5.0V)
VREF (2.7V)
Function
(Default=0)
13
VTO
O
14
ADVDD
VIN
15
ADGND
VIN
16
VSYNC/CSYS O
17
FODD/SRAM O
18
HREF/VSFRAM O
19
*_UV7/B8
O
20
*_UV6/TVEN
O
21
*_UV5/MIR
O
22
*_UV4/SLAEN
O
23
*_UV3/ECLK0
O
24
*_UV2/QSVGA
O
25
*_UV1/CC656
O
26
*_{UV0/GAMMA O}
27
XCLK1
I
28
XCLK2
O
29
DVDD
VIN
30
DGND
VIN
31
DOGND
VIN
32
DOVDD
VIN
33
PCLK/PWDB O
34
Y7
O
35
Y6
O
36
Y5/SHARP
O
37
Y4
O
Function/Description
Array power (+3.3VDC). Bypass to ground with a 0.1µF capacitor.
Chip reset, active high. Resets all control registers to factory defaults.
Automatic Gain Control (AGC) selection
“0” – Disable AGC
“1” – Enable AGC
Note: This function is disabled when OV8610/OV8110 sensor is configured in
SCCB low mode. In SCCB low mode this pin is an SCCB chip select function.
Frame exposure control
“0” – Disables frame exposure control
“1” – Enables frame exposure control
Array reference. Connect to ground with a 0.1µF (min.) capacitor.
Analog substrate voltage
Analog ground
Analog power supply (+3.3VDC). Bypass to ground with a 0.1µF capacitor.
Power-down mode selection.
“0” – Operating mode
“1” – Power-down mode
Charge pump out voltage. Doubler must be enabled.
Internal voltage reference. Bypass to ground with a 0.1µF capacitor.
SCCB enable selection.
“0” – Selects internal register setting control and enables SCCB interface
“1” – Enables I/O input pin power on latch setting control
B&W CCIR analog composite signal output—for test purposes only
Analog power supply (+3.3VDC). Bypass to ground with a 0.1µF capacitor.
Analog signal ground
Vertical sync output. At power-up, read as CSYS.
Field ID FODD output. At power-up, read as SRAM.
HREF output. At power-up, read as VSFRAM
Bit 7 of U video component output. At power-up, sampled as B8.
Bit 6 of U video component output. At power-up, sampled as TVEN.
Bit 5 of U video component output. At power-up, sampled as MIR.
Bit 4 of U video component output. At power-up, sampled as SLAEN.
Bit 3 of U video component output. At power-up, samples as ECLKO.
Bit 2 of U video component output. At power-up, sampled as QSVGA.
Bit 1 of U video component output. At power-up, sampled as CC656.
Bit 0 of U video component output. At power-up, sampled as GAMMA.
Crystal clock input
Crystal clock output
Digital power supply (+3.3VDC). Bypass to ground with a 0.1µF capacitor.
Digital ground
Digital interface output buffer ground
Digital output buffer supply (+3.3VDC ). Bypass to ground with a 0.1µF capacitor.
PCLK output. At power-up sampled as charge pump enable.
Bit 7 of Y video component output
Bit 6 of Y video component output
Bit 5 of Y video component output. At power-up, sampled as SHARP.
Bit 4 of Y video component output
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: [phone] Fax: [phone]
e-mail: [e-mail]
Website: http://www.ovt.com
Version 1.3, August 27, 2001
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