OV8610 Datasheet, PDF (16/28 Pages) List of Unclassifed Manufacturers – Advanced Information Preliminary

Advanced Information
Preliminary
OV8610/OV8110
OV8610 SINGLE-CHIP CMOS VGA COLOR DIGITAL CAMERA
OV8110 SINGLE-CHIP CMOS VGA B&W DIGITAL CAMERA
Frame Exposure Mode
OV8610/OV8110 supports frame exposure mode when FREX
is set high. PWDN is asserted by an external master device to
set exposure time at this mode. The pixel array is quickly pre-
charged when PWDN is set to “1”. OV8610/OV8110 captures
the image in the time period when PWDN remains high. The
video data stream is delivered to output port in a line-by-line
manner after PWDN switches to “0”.
It should be noted that PWDN must remain high long enough to
ensure the entire image array has been pre-charged.
Reset
OV8610/8110 includes a RESET pin (pin 2) that forces a
complete hardware reset when it is pulled high (VCC).
OV8610/8110 clears all registers and resets to their default
values when a hardware reset occurs. Reset can also be
initiated through the SCCB interface.
Power Down Mode
Two methods are available to place OV8610 into power-down
mode: hardware power-down and SCCB software power-down.
To initiate hardware power-down, the PWDN pin (9) must be
tied to high (+3.3VDC). When this occurs, the OV8610 internal
device clock is halted and all internal counters are reset. The
current draw is less than 10µA in this standby mode.
Executing a software power-down through the SCCB interface
suspends internal circuit activity, but does not halt the device
clock. The current requirements drop to less than 1mA in this
mode.
Configure OV8610/OV8110
The method to configure OV8610/OV8110 is to use its on-chip
SCCB register programming capability. The SCCB interface
provides access to all of the device’s programmable internal
registers.
FREX
T_IN
T_SET
HSYNC
Mechanical Shutter Off
T_HS
Precharge begins at the rising edge of HSYNC
ARRAY
PRECHARGE
DATA
OUTPUT
T_PR
Array Exposure Period T_EX
Array Precharge Period T_PR
1 Frame (612 Lines) Valid Data
Invalid Data
Black Data
VSYNC
T_HD Head of Valid Data (8 Lines)
Next Frame
HREF
Note:
# T_PR=824 x 4 x T_CLK or T_PR=858xT_clk depends on mode selecton. T_CLK is internal pixel period. T_CLK=50ns
#
#
#
if the system clock is 20MHz . T_CLK will increase with the clock divider CLK[5:0].
T_EX is array exposure time which is decided by external master device.
T_IN is uncertain time due to the using of HSYNC rising edge to synchronize FREX. T_IN < T_HS.
There are 8 lines data output before valid data after FREX=0. T_HD=4 THS. Valid data is output when
HREF=1.
# T_SET=T_IN + T_PR + T_EX. T_SET > T_PR + T_IN. The exposure time setting resolution is T_HS (one line) due to the
uncertainty of T_IN.
Figure 8. Frame Exposure Timing
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: [phone] Fax: [phone]
e-mail: [e-mail]
Website: http://www.ovt.com
Version 1.3, August 27, 2001
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