ICS94222 Datasheet, PDF (2/19 Pages) List of Unclassifed Manufacturers – Programmable System Frequency Generator for PII/III™

ICS94222
Advance Information
Pin Configuration
PIN NUMBER
1
2
3
PIN NAME
AVDD
REF1
FS2¹
REF0
PCI_STOP#¹
4, 10, 23, 26, 34, 42,
48, 53
GND
5
X1
6
7, 15, 20,
37, 45
8
9
X2
VDD
PCICLK_F
MODE¹
FS3¹
PCICLK0
TYPE
PWR
OUT
IN
OUT
IN
DESCRIPTION
Analog power supply 3.3V
14.318 MHz reference clock output
Latched frequency select input. Has pull-up to VDD
14.318MHz reference clock output
Halts PCICLK [5:1] at logic "0" level when low.
(in mobile, MODE=0)
PWR Ground.
IN
OUT
PWR
OUT
IN
IN
OUT
14.318MHz input. Has internal load cap, (nominal 33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
Nominal 3.3V power supply, see power groups for function.
Free running BUS clock not afected by PCI_STOP#
Latched input for MODE select. Converts pin 3 to PCI_STOP# when
low for power management.
Latched frequency select input, pull-down
Free running BUS clock not afected by PCI_STOP#
16, 14, 13, 12, 11 PCICLK (5:1)
OUT PCI Clock Outputs.
17
BUFFERIN
27
SDATA
28
SCLK
24MHz
30
FS0¹
48MHz
29
FS1¹
IN
IN
IN
OUT
IN
OUT
IN
Input for Buffers
Serial data in for serial config port. (I²C)
Clock input for serial config port. (I²C)
24MHz clock output for Super I/O or FD.
Latched frequency select input. Has pull-up to VDD
48MHz clock output for USB, 2X strength.
Latched frequency select input. Has pull-up to VDD
31
AVDD48
PWR Analog power supply 3.3V
24, 25, 32, 33, 18,
19, 21, 22, 35, 36,
38, 39, 40, 41, 43,
44
SDRAM (15:0)
OUT SDRAM clocks
46
SDRAM_F
OUT Free running SDRAM clock Not affected by CPU_STOP#
47
50, 56
CLK_STOP#
VDDL
IN
PWR
Halts CPUCLKs, IOAPIC0, SDRAMs
clocks at logic "0" level when low.
CPU and IOAPIC clock buffer power supply, 2.5V nominal.
55
49, 51
52
54
IOAPIC0
CPUCLK (1:0)
CPUCLK_F
IOAPIC_F
OUT
OUT
OUT
OUT
IOAPIC clock output. (14.318 MHz) Poweredby VDDL
CPU Output clocks. Powered by VDDL (60 or 66.6MHz)
Free running CPU output clock. Not affected ty the CLK_STOP#.
Freerunning IOAPIC clock output. Not affected by the CLK_STOP#
(14.31818 MHz) Powered by VDDL
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
This document is confidential and should not be released
without written consent from ICS.
2