FX623 Datasheet, PDF (2/6 Pages) List of Unclassifed Manufacturers – Call Progress Tone Decoder

Pin Number
Function
FX623P
1
Q3: Data Outputs: A 4-bit parallel data word, forming a HEX character representing the
2
Q2: decoded tone frequency. This word is output after a successful decode. Table 1 details the
3
Q1: Hex character output codes for the relevant decoded tone frequencies. Upon power-up this
4
Q0: output is set to ‘E_H’, but no Data Change pulse generated. These are tri-state outputs.
5
V_DD: Positive supply rail. A minimum supply voltage of 3.0 volts is required. Levels and voltages within
this decoder are dependent upon this supply.
6
Signal In: The composite audio input. Signals to this pin should be a.c. coupled. The d.c. bias of the
limiter section is set internally; this pin should not be loaded with any other circuitry.
7
No internal connection. Leave open circuit.
8
Xtal: The output of the on-chip clock oscillator inverter.
9
No internal connection. Leave open circuit.
10
Xtal/Clock: The input to the clock oscillator inverter. A 3.579545MHz Xtal or externally derived clock
should be connected here (see Figure 2).
11
V : Negative supply rail (GND).
SS
12
Hold: An input to control the Output Latch condition; employed in combination with the Data Change
output to facilitate, if required, Interrupt and/or handshake operations with a µProcessor.
With Hold placed “Low”, with a tone input, the Data Change output will be held “High” at the next data
change, and the current output code is locked in the Output Latches regardless of any changes to the
input signal.
The output code remains as held until this input is returned “High” (see Figure 3). Whilst this input is
“High” the output data, Q0 - Q3, cycles normally with the input audio.
This pin has an internal 1.0MΩ pullup resistor.
13
PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic “1” level is required at this pin
for a duration of at least 2.5mS after the Xtal/Clock input and full V_DD levels are applied.
The component configuration shown in Figure 2 is recommended; for slow-rising power supplies the
time constant of components should be increased accordingly.
14
IRQ: Interrupt Request. An output for µProcessor operation; normally “High” this output is latched
“Low” when an internal data change occurs if the Chip Select input is “High”. This output is reset
(“High”) the when Chip Select line is taken “Low”.
To permit “wire-OR” connection with other peripherals, this output has a low-impedance when “Low”
and a high-impedance when “High”.
15
CS: Chip Select- A controlling function. When held “High” the Data Outputs Q0, Q1, Q2 and Q3 and
the Data Change output are disabled.
When taken “Low” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are enabled;
the Interrupt Request (IRQ) is reset (“High”) when CS is taken “Low”. See Figures 3 and 4.
16
Data Change: A positive-going pulse is generated at this output when the data changes (Tone or
NOTONE). New tone-data is presented to the Q0, Q1, Q2 and Q3 Data Outputs if the Hold input is set
“High”. This is a tri-state output.
2