3D3428 Datasheet, PDF (2/7 Pages) List of Unclassifed Manufacturers – MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

3D3428
APPLICATION NOTES
GENERAL INFORMATION
The 8-bit programmable 3D3428 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (OUT)
by the user-selected programming data (the
address). Each delay cell produces at its output a
replica of the signal present at its input, shifted in
time. The change in delay from one address
setting to the next is called the increment, or
LSB. It is nominally equal to the device dash
number. The minimum delay, achieved by setting
the address to zero, is called the inherent delay.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
DELAY ACCURACY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the differential nonlinearity (DNL), also referred
to as the increment error. It is defined as the
deviation of the increment at a given address
from its nominal value. For most dash numbers,
the DNL is within 0.5 LSB at every address (see
Table 1: Delay Step).
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The relative error is defined as follows:
e_rel = (T_i – T₀) – i * T_inc
where i is the address, T_i is the measured delay
at the i’th address, T₀ is the measured inherent
delay, and T_inc is the nominal increment. It is very
similar to the INL, but simpler to calculate. For
most dash numbers, the relative error is less than
1.0 LSB at every address (see Table 1: Delay
Range).
The absolute error is defined as follows:
e_abs = T_i – (T_inh + i * T_inc)
where T_inh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 3.0 ns,
whichever is greater, at every address.
The inherent delay error is the deviation of the
inherent delay from its nominal value. It is limited
to 1.0 LSB or 2.0 ns, whichever is greater.
DELAY STABILITY
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D3428 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
With regard to stability, the delay of the 3D3428
at a given address, i, can be split into two
components: the inherent delay (T₀) and the
relative delay (T_i – T₀). These components exhibit
very different stability coefficients, both of which
must be considered in very critical applications.
The thermal coefficient of the relative delay is
limited to ±250 PPM/C (except for the dash 0.25),
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% (±9% for the
dash 0.25) from the room-temperature delay
settings. The thermal coefficient of the inherent
delay is nominally +20ps/C for dash numbers 5
or less, and +30ps/C for all other dash numbers.
The power supply sensitivity of the relative delay
is ±1.0% (±3.0% for the dash 0.25) over the 3.0V
to 3.6V operating range, with respect to the delay
settings at the nominal 3.3V power supply. This
holds for all dash numbers. The sensitivity of the
inherent delay is nominally –5ps/mV for all dash
numbers.
INPUT SIGNAL CHARACTERISTICS
The frequency and/or pulse width (high or low) of
operation may adversely impact the specified
delay and increment accuracy of the particular
device. The reasons for the dependency of the
output delay accuracy on the input signal
characteristics are varied and complex.
Therefore a recommended maximum and an
absolute maximum operating input frequency and
a recommended minimum and an absolute
minimum operating pulse width have been
specified.
OPERATING FREQUENCY
The absolute maximum operating frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
Doc #04004
DATA DELAY DEVICES, INC.
2
11/1/04
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