MTV230M64 Datasheet, PDF (19/31 Pages) List of Unclassifed Manufacturers – 8051 Embedded Micro Controller with Flash OSD and ISP

MTV230M64
Repeat Line Number of character
Repeat Line
Repeat Line #
Weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1
- - - - - - - -v- - - - - - - - -
+2
- - - -v- - - - - - -v- - - - -
+4
- -v- - -v- - -v- - -v- - -
+8
-v-v-v-v-v-v-v-v- -
+16
- vvvvvvvvvvvvvvvv -
+17
vvvvvvvvvvvvvvvvv -
+18
vvvvvvvvvvvvvvvvvv
Note: “v” means the nth line in the character would be repeated once, while “-“ means the nth line in the
character would not be repeated.
11.3 Display RAM
The display RAM contains character address, attribute and row control registers. The display registers have 450
locations which are allocated between (row 0, column 0) to (row14, column 29). Each display register has its
corresponding character address on ADDRESS bytes, and its corresponding color, blink bit, background color
on ATTRIBUTE bytes. The row control register is allocated at column 30 from row 0 to row 14 of address bytes.
It is used to set character size to each respective row. If double width character is chosen, only even column
characters could be displayed on screen and the odd column characters will be hidden.
There are 4 registers to program display RAM: OSDRA, OSDCA, OSDDT0 and OSDDT1. OSDRA is the row
address; OSDCA is the column address; OSDDT0 and OSDDT1 are the programming data byte. The 2 MSB
(bit 7 - bit 6) of OSDRA register are used to distinguish ADDRESS byte when they are set to “0, 0” and
ATTRIBUTE byte when they are set to “0, 1”. OSDDT0 and OSDDT1 are used to differentiate the MSB (bit 8) of
display characters address. The MSB (bit 8) of display characters address will be equal to ”0“ while data byte is
filled into OSDDT0, or “1” while data byte is filled into OSDDT1; and OSDDT0 or OSDDT1 are the 8 LSB (bit 7 -
bit 0) of display characters address.
The programming row (OSDRA) and column (OSDCA) address of display RAM will be incremented
automatically when MCU continues to update OSDDT0 or OSDDT1. It is used to save the program ROM size of
MCU while massive data update or full screen data change.
Since bit 8 is fixed on OSDDT0 (OSDDT1) while programming ADDRESS byte, the continued OSDDT0
(OSDDT1) will be the same bank of lower 256 fonts (upper 256 fonts) until program another data byte OSDDT1
(OSDDT0) register.
To program ADDRESS bytes and ATTRIBUTE bytes of the display RAM:
Step 1. Write data into OSDRA to determine the programming row address of the display RAM. And define it
is the row address of ADDRESS byte (bit7-bit6 = “0, 0”) or ATTRIBUTE byte (bit7-bit6 = “0, 1”).
Step 2. Write data into OSDCA to determine the programming column address of the display RAM.
Step 3. Write to OSDDT0 or OSDDT1 the address or attribute of the character to be displayed on the screen.
Step 4. Post increment operation is executed in the OSDCA (i.e. OSDCA ← OSDCA + 1) to make it point to
the next display RAM location. Overflow of the OSDCA, i.e. overflow from 31, makes itself return to 0
and makes post increment operation executed in the OSDRA (i.e. OSDRA ← OSDRA + 1). Overflow
of the OSDRA, i.e. overflow from 15, makes itself return to 0.
It is the step 3 which triggers the load of OSDDT0 or OSDDT1 into the current OSDRA, OSDCA address of the
display RAM and the post increment operation. Furthermore, the undefined locations in the display RAM should
be filled with dummy data while post increment operation is executed.
So there are three transmission formats shown as below:
Format (a) R-C-D->R-C-D->R-C-D…
Format (b) R-C-D->C-D->C-D->C-D…
Format (c) R-C-D->D->D->D->D->D…
Where R=OSDRA (row address), C=OSDCA (column address), D=OSDDT0 or OSDDT1 (display data)
Format (a) is suitable for updating small amount of data which will be allocated with different row address and
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