MTV230M64 Datasheet, PDF (12/31 Pages) List of Unclassifed Manufacturers – 8051 Embedded Micro Controller with Flash OSD and ISP

MTV230M64
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] x 0.167 µs for 12MHz X’tal selection.
HVCTR4 (w): HSYNC digital filter control register.
DF =0
→The digital filter will treat any HSYNC pulse shorter than one OSC period (83.33ns)
as noise, between one and two OSC period (83.33ns to 166.67ns) as unknown
region, and longer than two OSC period (166.67ns) as pulse.
=1
→Disable the digital filter for HSYNC.
INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serve the interrupt routine.
HPRchg= 1 → No action.
= 0 → Clear HSYNC presence change flag.
VPRchg= 1 → No action.
= 0 → Clear VSYNC presence change flag.
HPLchg= 1 → No action.
= 0 → Clear HSYNC polarity change flag.
VPLchg = 1 → No action.
= 0 → Clear VSYNC polarity change flag.
HFchg = 1 → No action.
= 0 → Clear HSYNC frequency change flag.
VFchg = 1 → No action.
= 0 → Clear VSYNC frequency change flag.
Vsync = 1 → No action.
= 0 → Clear VSYNC interrupt flag.
INTFLG (r) : Interrupt flag.
HPRchg= 1 → Indicates a HSYNC presence change.
VPRchg= 1 → Indicates a VSYNC presence change.
HPLchg= 1 → Indicates a HSYNC polarity change.
VPLchg = 1 → Indicates a VSYNC polarity change.
HFchg = 1 → Indicates a HSYNC frequency change or counter overflow.
VFchg = 1 → Indicates a VSYNC frequency change or counter overflow.
Vsync = 1 → Indicates a VSYNC interrupt.
INTEN (w) : Interrupt enable.
EHPR = 1 → Enable HSYNC presence change interrupt.
EVPR = 1 → Enable VSYNC presence change interrupt.
EHPL = 1 → Enable HSYNC polarity change interrupt.
EVPL = 1 → Enable VSYNC polarity change interrupt.
EHF = 1 → Enable HSYNC frequency change / counter overflow interrupt.
EVF = 1 → Enable VSYNC frequency change / counter overflow interrupt.
EVsync = 1 → Enable VSYNC interrupt.
7. DDC & IIC Interface
7.1 DDC2B Mode
To perform DDC2 function, S/W can config the Slave A IIC block to act as EEPROM behavior. The Slave A
block's slave address can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W choose 5-bits slave
address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2 LSB "xx" in
XFR. This feature enables MTV230M64 to meet PC99 requirement.
7.2 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using IIC
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