STAC9460 Datasheet, PDF (18/21 Pages) List of Unclassifed Manufacturers – Two and Six-Channel, 24-Bit, 192 kHz Audio Codec

PRELIMINARY INFORMATION 8/24/01
STAC9460/62
Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
7.1.10.
Powerdown Control Registers (10h-11h)
The STAC9460 is capable of operating at reduced power when no activity is
required. The state of power down is controlled by the Powerdown register. There
are 11 separate power down commands. The Powerdown options are listed in Table
21. The bits can be used individually or in combination with each other, and control
power distribution to the ADC’s and DAC’s. If the VREF option is selected it powers
down the entire chip. Please note the rear, center, ad bass DAC’s should be pow-
ered down for operation with the STAC9462.
REG 11H
REG 10H
BIT
FUNCTION
BIT
FUNCTION
D0: PLF
D1: PRF
DAC_LF
DAC_RF
D0: DIFF
D1: DIG
Differential
Powers down I²S
and De-emphasis
D2: PLR
DAC_LR
D2: VREF
Voltage Reference
D3: PRR
DAC_RR
D3: ADC Bias
Powerdown ADC
Bias circuitry
D4: PCTR
DAC_CTR
D4:
X
D5: PLFE
DAC_LFE
D5:
X
D6: ADL
ADC Left
D6:
X
D7: ADR
ADC Right
D7:
X
* Note: Powers down I²S and De-emphasis
X: denotes reserved
Table 18. Powerdown Control
7.1.11.
Revision Code Register (12h)
The device Revision register contains a software readable revision-specific code
used to identify performance, architectural, or software differences between various
device revisions.
7.1.12.
Address Control Register/Address Register (13h-14h)
The address for the chip is defaulted to 55/56 or 54/55 for read and write. The LSB
(bit D1) is programmable with the CS, pin 10. The Address Register (14h) can be
changed. To change the address, AB must first be written to The Address Control
Register (13h). A soft or hard reset will reset the Address Register to its default
value with CS representing the LSB (D1).
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2-9460-D1-1-0-0801