STAC9460 Datasheet, PDF (17/21 Pages) List of Unclassifed Manufacturers – Two and Six-Channel, 24-Bit, 192 kHz Audio Codec

PRELIMINARY INFORMATION 8/24/01
STAC9460/62
Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
7.1.9.
Master Clocking Register (0Fh)
The Master Clocking Register is used to set the sampling rate of the converters to
one of the three sample rate modes. Base rate, mid rate and high rate are selected
with bits D1-D0 of the register. The master clock mode is set by selecting bits
D4,,D2. The master clock mode is used generate an internal clock of the correct
frequency based on the MCLK supplied by the user. For example, in the default
mode (MCM=100 and SRM=00), MCLK in 512x, so if the sample rate is 48kHz then
MCLK must be at 24.576MHz, which is 512x48kHz. Or with MCM=011 and
SRM=01 (Mid Rate Mode) and a sample rate of 96kHz, then MCLK must be at
192x96kHz which is 18.432MHz. THe Master CLocking Register should be set
before unmuting any DAC or ADC channels in register 02h to 0Ah. MCM2 (D4) set
is default mode.
SRM1SRM0
D1,D0
00 (default)
01
10
11
SAMPLE RATE
SR ≤ 48 kHz
48 kHz < SR ≤ 96 kHz
96 kHz < SR ≤ 192kHz
Reserved
FUNCTION
Base Rate Mode
Mid Rate Mode
High Rate Mode*
Reserved
Note:*ADC operates in Mid Rate Mode when High Rate Mode is selected, and will
send each sample for two successive I2S frames.
Table 16. Sample Rate Mode
MCM2 .. MCM0
D4,D3,D2
BRM
MCLK Mode*
MRM
HRM
000
128x
64x
32x
001
Reserved
Reserved
Reserved
010
256x
128x
64x
011
384x
192x
96x
100 (default)
512x
256x
128x
101
768x
384x
192x
110
Reserved
Reserved
Reserved
111
Reserved
Reserved
Reserved
*Note: MCLK rate is relative to sample rate. (MCM * SR = MCLK). The number of
D_SCLKs/D_LRCLK is independant of the MCLK mode for the STAC9460/62, but
most controllers will generate D_SCLK at 1/2, 1/4, 1/8, or 1/16 the MCLK rate.
Table 17. MCLK Mode
2-9460-D1-1-0-0801
17