TC5747 Datasheet, PDF (17/44 Pages) List of Unclassifed Manufacturers – Single Chip CMOS Imager with Integrated Image Signal Processor and JPEG Codec

TC5747 Preliminary Data Sheet
Single Chip CMOS Imager
3. Reset and Clock
3.1 Low Power Modes
The chip operation is controlled by two bits [PS1, PS2]:
Chip operation modes [PS1, PS2]:
00 – Startup
01 – Full operation
11 – Sleep
10 – Power down
3.1.1 Startup
The camera powers up at start up mode “ 00” . Then it moves to full operation mode “ 01” .
3.1.2 Bypass
To enter bypass mode, send a host command for power save, then provide standby mode “ 11” or switch off
the input clock. Bypass mode power consumption is 60µA. This minimum power is consumed by a minimal
power-supply digital regulator. Contents of memories and registers are maintained. The host can access the
LCD during bypass mode.
To return to full operation from standby mode, switch on the input clock and wait for clock stability, then
send a host command for full operation.
3.1.3 Power Down
To enter power down mode, send a host command for power down, and then provide power down mode
“ 10” . Power down mode consumes less than 10µA.
To return to full operation from power down mode: provide full operation mode “ 01” , wait for clock
stability, then send a host command for full operation and load the camera program.
3.2 PLL Configurations
An on-chip PLL is configured to supply the internal working clock signal in several modes:
Bypass mode – internal clock is identical in frequency to input clock.
PLL mode, for support of an internal clock in the range of 24-36MHx
8x – internal clock is 8x the input clock, for support of low frequency input (3-4MHz input)
4x – internal clock is 4x the input clock, for support of low frequency input (8-9MHz input)
2x - internal clock is 2x the input clock, for support of medium frequency input (13-16MHz input)
1.5x - internal clock is 1.5x the input clock, for support of high frequency input (20-24MHz input)
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