EX128 Datasheet, PDF (17/36 Pages) List of Unclassifed Manufacturers – eX Family FPGAs

eX Family FPGAs
eX Family Timing Characteristics (Continued)
(Worst-Case Commercial Conditions V_CCA = 2.3V, V_CCI = 4.75V, T_J = 70°C)
‘–P’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Networks
t_HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
t_HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
t_HPWH
Minimum Pulse Width HIGH
t_HPWL
Minimum Pulse Width LOW
t_HCKSW
Maximum Skew
t_HP
Minimum Period
f_HMAX
Maximum Frequency
Routed Array Clock Networks
1.1
1.6
2.3
ns
1.1
1.6
2.3
ns
1.4
2.0
2.8
ns
1.4
2.0
2.8
ns
<0.1
<0.1
<0.1 ns
2.8
4.0
5.6
ns
357
250
178 MHz
t_RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.6
2.2
ns
t_RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
t_RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
t_RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
t_RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
t_RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
t_RPWH
Min. Pulse Width HIGH
1.5
2.1
3.0
ns
t_RPWL
t_RCKSW1
t_RCKSW1
t_RCKSW1
Min. Pulse Width LOW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
2.1
3.0
ns
0.2
0.3
0.4
ns
0.1
0.2
0.3
ns
0.1
0.1
0.2
ns
Note:
1. Clock skew improves as the clock network becomes more heavily loaded.
v3.0
17