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EX128 Datasheet, PDF (16/36 Pages) List of Unclassifed Manufacturers – eX Family FPGAs
eX Family FPGAs
eX Family Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.3V, TJ = 70°C)
‘–P’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
C-Cell Propagation Delays1
Min. Max. Min. Max. Min. Max. Units
tPD
Internal Array Module
Predicted Routing Delays2
0.7
1.0
1.4
ns
tDC
FO=1 Routing Delay, DirectConnect
tFC
FO=1 Routing Delay, FastConnect
tRD1
FO=1 Routing Delay
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
tRD12
FO=12 Routing Delay
R-Cell Timing
0.1
0.1
0.2
ns
0.3
0.5
0.7
ns
0.3
0.5
0.7
ns
0.4
0.6
0.8
ns
0.5
0.8
1.1
ns
0.7
1.0
1.3
ns
1.2
1.7
2.4
ns
1.7
2.5
3.5
ns
tRCO
Sequential Clock-to-Q
tCLR
Asynchronous Clear-to-Q
tPRESET
Asynchronous Preset-to-Q
tSUD
Flip-Flop Data Input Set-Up
tHD
Flip-Flop Data Input Hold
tWASYN
Asynchronous Pulse Width
tRECASYN
Asynchronous Recovery Time
tHASYN
Asynchronous Hold Time
2.5V Input Module Propagation Delays
0.6
0.9
1.3
ns
0.6
0.8
1.2
ns
0.7
0.9
1.3
ns
0.5
0.7
1.0
ns
0.0
0.0
0.0
ns
1.3
1.9
2.6
ns
0.3
0.5
0.7
ns
0.3
0.5
0.7
ns
tINYH
Input Data Pad-to-Y HIGH
tINYL
Input Data Pad-to-Y LOW
3.3V Input Module Propagation Delays
0.6
0.9
1.3
ns
0.8
1.1
1.5
ns
tINYH
Input Data Pad-to-Y HIGH
tINYL
Input Data Pad-to-Y LOW
5.0V Input Module Propagation Delays
0.7
1.0
1.4
ns
0.9
1.3
1.8
ns
tINYH
Input Data Pad-to-Y HIGH
tINYL
Input Data Pad-to-Y LOW
Input Module Predicted Routing Delays2
0.7
1.0
1.4
ns
0.9
1.3
1.8
ns
tIRD1
FO=1 Routing Delay
0.3
0.4
0.5
ns
tIRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tIRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tIRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tIRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tIRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
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