MTD658E Datasheet, PDF (16/23 Pages) List of Unclassifed Manufacturers – 5/8 Port 10/100 Hub Build_in Bridge And Memory

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MTD658E
nous with ICLK. The MTD658E output REQOUT to inform Inter-Bus Interface that it need the Inter-Bus
right. When IACKB is asserted by Inter-Bus master after REQOUT asserted, the MTD658E which
asserted REQOUT will get the bus right and put the transmit data into IDATA. If the MTD658E did not
assert REQOUT , but IACKB is asserted, means this MTD658E can get data from IDATA bus. When
only one MTD658E output REQOUT to Inter-Bus Interface, IACKB will be asserted by Inter-Bus master
device, If larger than two MTD658E’s REQOUT were asserted, Inter-Bus master will not assert IACKB ,
but will assert ICOLB to inform all the connected MTD658Es.
The Inter-Bus interface can also be programmed to EXT_ARB mode, using LEDDAT pin’s jumper set-
ting. In this mode, Inter-Bus interface need an external arbitration logic to arbitrate Inter-Bus operation.
And in this mode, the stackable capability is not limitted by the MTD658E’s REQIN pins number.
5.6 10M/100M packet Switch
The MTD658E inplements a 10/100M two port switch for 10M/100M packet switching. Total 2K address
entrys are provided for packets’SA learning and DA routing; and alsoprovide automatic aging function
( aging time = 300secs). The input packet from 10MHub ( or 100M Hub) will be stored to external
memory first, while packet is good for forward ( CRC chech ok, length = 64Bytes ~ 1518Bytes or 1522
Bytes, and not local packets ) , than forward this packet to 100M Hub (or 10M Hub).
5.7 Uplink Switch Port
The MTD658E can config one switch port as an uplink switch port. When UPSWEN pin is high, and
IMASTER pin is low, one of the intenal switch port is connect to 100M Hub, the other is connected to
RMII the highest port . In uplink switch mode, the highest port can operate in 10M/100M (in 8 port mode
: from SPD7 pin; in 5 port mode: from SPD4 pin ), and operate in half/full duplex (in 8 port mode: from
FD7 pin; in 5 port mode: from FD4 pin).
5.8 Memory Interface
The MTD658E build-in an asynchronous SRAM as two port switchs’packet buffers, total has 64K byte
embedded memory for packet buffering.
5.9 MII management
The MTD658E can be managed through MDC, MDIO pins. The MTD658E implements 3 MII registers
for function control and status report (see Section 4.0 on page ).
The management frame format is compliant to IEEE802.3u clause 22, and the device ID is fixed to
5’h1f internally.
5.10 LED display
The MTD658E implements three display modes, port RX activity, 10/100M domain collision, port parti-
tion. The LED data pin LEDDAT is high actived.
One strobe pin LEDCLK(24 burst clock/per 42ms) is used to latch serial LEDDAT information, and user
can shift the latched data into byte aligned shift register to drive LEDs.
The MTD658E also provide status pins to direct output per port’s receive activity/partition, 100M Hub
collision, 10M Hub collision, embedded ASRM memory test fail status.
6.0 Registers
The MTD658E implements 3 MII registers, define as following tables:
TABLE 1. MII r egister s
REG
NO
Bits
0
0
1
Name
CtlReg0
DisPar10
R/W
Descriptions
R/W
CONTROL REGISTER 0
Reserved.
Set this bit will disable 10M hub core partition function.
Default
1b0
1b0
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MTD658E Revision 1.1 05/25/2000