MTD658E Datasheet, PDF(12/23 Page) List of Unclassifed Manufacturers – 5/8 Port 10/100 Hub Build

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MTD658E Datasheet, PDF (12/23 Pages) List of Unclassifed Manufacturers – 5/8 Port 10/100 Hub Build_in Bridge And Memory

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MYSON

TECHNOLOGY

MTD658E

Name

ICLK100

IDAT100_0

IDAT100_1

IDAT100_2

IDAT100_3

100M Inter-Bus Interface pins (for 5 port mode)

Pin Number

I/O

Descriptions

I/O 100M Inter-Bus port clock.

I/O 100M Inter-Bus port data bit 0.

I/O 100M Inter-Bus port data bit 1.

I/O 100M Inter-Bus port data bit 2.

I/O 100M Inter-Bus port data bit 3.

Name

RXACT4-0

PART4-0

XCOL100

XCOL10

LEDDAT

Pin Number

90,91,93,94,

99,100,101,

102,104

109

110

124

LED Interface Pins (for 5 port mode)

I/O

Descriptions

I/O Port 4-0 Rx Activity LED Outputs, low_active.

Direct output per port receive activity status for LED display.

I/O Port 4-0 Partition LED Outputs, low_active.

Direct output per port partition status for LED display. During power on

reset PART4 pin use as MII setting start PHY device ID selection. 4.7K

pull up resistor will set PHY device ID from 5h08 - 5h0f, no pull up 4.7k

resistor will set PHY device ID from 5h04 -5h0b.

I/O 100M Hub Collision LED Output, low_active.

I/O 10M Hub Collision LED Output, low_active.

I/O LED display serial data out, high_active; mapping for LEDCLK sig-

nalâs burst clock , its serial out data sequence is : ( first bit be shifted out

is from b00, and end of burst bit is b23)

b00: *********** b08: 10hub_col

b16: ************

b01: ********** b09: 100hub_col

b17: ************

b02: ********** b10: asram_test_fail b18: ************

b03: port0 partition b11: port0 partition b19: port0 rx_activity

b04: port1 partition b12: port1 partition b20: port1 rx_activity

b05: port2 partition b13: port2 partition b21: port2 rx_activity

b06: port3 partition b14: port3 partition b22: port3 rx_activity

b07: port4 partition b15: port4 partition b23: port4 rx_activity

LEDCLK

I/O LED display clock signal, the signal is a discontinued clock for LED

125

data serial shift out. Every clock burst have 24 cycles ( period : 160 ns),

and the clock burst will be repeated with every 42ms.

Miscellaneous Pins (for 5 port mode)

Name Pin Number I/O

Descriptions

RSTB

128

I System reset input, low active.

SYSCLK

122

I 50MHz system clock input

CLK25MOUT

114

I/O 25MHz clock output.

MDC

126

I/O MII management clock inout

MDIO

127

I/O MII management data inout

12/23

MTD658E Revision 1.1 05/25/2000

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