GS832218 Datasheet, PDF (16/41 Pages) List of Unclassifed Manufacturers – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Preliminary
GS832218(B/E)/GS832236(B/E)/GS832272(C)
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
W
First Read ^X
CW
CR
W
X
R
Burst Write
CR
CW
R
W
Burst Read ^X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.06 9/2004
16/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology