MSP3405D Datasheet, PDF (15/71 Pages) List of Unclassifed Manufacturers – Multistandard Sound Processors

PRELIMINARY DATA SHEET
MSP 34x5D
4.6. I²S Bus Interface
By means of this standardized interface, additional fea-
ture processors can be connected to the MSP 34x0D.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I2S_WS signal changes at the word bound-
aries. The PHILIPS format, which is characterized by a
change of the I2S_WS signal one I2S_CL period before
the word boundaries, is selected by setting
MODE_REG[4]=1.
The MSP 34x5D normally serves as the master on the
I²S interface. Here, the clock and word strobe lines are
driven by the MSP. By setting MODE_REG[3]=1, the
MSP 34x5D is switched to a slave mode. Now, these
lines are input to the MSP and the master clock is syn-
chronized to 576 times the I2S_WS rate (32 kHz). NI-
CAM operation is not possible in this mode.
The I²S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2:
For input, four channels (two channels per line, 2*16
bits) per sampling cycle (32 kHz) are transmitted.
2. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling
cycle (32 kHz) are transmitted.
3. I2S_CL:
Gives the timing for the transmission of I²S serial data
(1.024 MHz).
4. I2S_WS:
The I2S_WS word strobe line defines the left and right
sample.
A precise I²S timing diagram is shown in Fig. 4–6.
(Data: MSB first)
I2S_WS
1/F_I2SWS
SONY Mode
PHILIPS Mode
PHILIPS/SONY Mode programmable by MODE_REG[4]
I2S_CL
I2S_DAIN R LSB L MSB
Detail A
16 bit left channel
I2S_DAOUT R LSB L MSB
Detail B
16 bit left channel
SONY Mode
PHILIPS Mode
Detail C
L LSB R MSB
L LSB R MSB
16 bit right channel
16 bit right channel
R LSB L LSB
R LSB L LSB
Detail C
I2S_CL
1/F_I2SCL
T_I2SWS1
T_I2SWS2
I2S_WS as INPUT
T_I2S5
T_I2S6
I2S_WS as OUTPUT
Fig. 4–6: I²S bus timing diagram
Micronas
Detail A,B
I2S_CL
I2S_DA_IN
I2S_DA_OUT
T_I2S1
T_I2S3
T_I2S2
T_I2S4
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