YMU759 Datasheet, PDF (12/18 Pages) List of Unclassifed Manufacturers – SYNTHESIS LSI FOR PORTABLE TELEPHONE

YMU759
Parallel I/F (write cycle)
Item
Symbol
Min.
Max.
Unit
Chip select width
Address setup time
TCSW
100
ns
TAS
10
ns
Address hold time
TAH
10
ns
Write pulse width
Data setup time
TWW
50
ns
TWDS
30
ns
Data hold time
TWDH
5
ns
Note: T_OP=-20 ~ 85°C, VDD=3.0±0.3 V, Capacitor load=50 pF.
(Read cycle)
Item
Symbol Min.
Max.
Unit
Chip select width
Address setup time
Address hold time
TCSR
100
ns
TAS
0
ns
TAH
0
ns
Read pulse width
Read data access time
TRW
80
TACC
ns
70
ns
Data hold time
TRDH
10
50
ns
Note: T_OP=-20 ~ 85°C, VDD=3.0±0.3 V, Capacitor load=50 pF.
Write cycle
A0
/CS
/WR
D0~D7
TCSW
TAH
TAS
TWW
Invalid
TWDS
TWDH
Valid
Invalid
Note: T_CSW, T_WW, T_WDH and T_AH are defined with respect to the moment /CS or /WR becomes High level.
Measurement point
VIH = 0.7*VDD
VIL = 0.2*VDD
VOH= 0.8*VDD
VOL = 0.4V
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