YMU759 Datasheet, PDF (10/18 Pages) List of Unclassifed Manufacturers – SYNTHESIS LSI FOR PORTABLE TELEPHONE

YMU759
Serial I/F
Item
Symbol
Min.
Typ.
Max. Unit
SCLK clock period
Tclk_period
80
ns
SCLK “L” pulse width
Tclk_low
20
ns
SCLK “H” pulse width
Tclk_high
20
ns
SCLK rise time
Trise_clk
30
ns
SCLK fall time
Tfall_clk
30
ns
SYNC “H” pulse width
Tsync_high
30
-
ns
SYNC “L” pulse width
Tsync_low
30
ns
SYNC / SDIN rise time
Trise
30
ns
SYNC / SDIN fall time
Tfall
30
ns
SYNC delay time
Tdelay_SYNC
0
ns
SYNC -> SCLK setup time
Tsetup_SYNC
120
ns
SDIN setup time
Tsetup_SDIN
20
ns
SDIN hold time
Thold_SDIN
20
ns
SDOUT delay time
Tdelay_SDOUT
70(*2)
ns
Read wait time
Trd_wait
(*1)
ns
Note: T_OP=-20 ~ 85°C, VDD=3.0±0.3 V, Capacitor load=50 pF.
(*1): Read wait time varies in the register which accesses it.
(*2): Max 70ns is the delay time when it is outputted from the D5 terminal.
Delay time from the SDOUT terminal varies according to pull-up resistance value and the load capacity of the
outside.
Standard delay time can be calculated by step response expression of the RC circuit.
Time to change to the voltage of [power supply of external pull-up resistance × 80%] is as follows.
1 - exp ( -t / R * C ) = 0.80
When R = 1kΩ, C= 50pF, t = 80ns //
"Standard delay time" and the reason why it was written are because resistance value and capacity value swing by
the part's own error and the temperature character.
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