SA25C512 Datasheet, PDF (12/19 Pages) List of Unclassifed Manufacturers – 512Kb EEPROM SPI with 10MHz and Low Standby

Table 9. Read Status Register Definition
Bit
Definition
Bit 0 (/RDY)
Bit 0 = 0 (/RDY) indicates that the
device is READY.
Bit 0 = 1 indicates that a write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates that the device is
not write enabled.
Bit 1 = 1 indicates that the device is
write enabled.
Bit 2 (BP0)
Block Write Protect Bit 0
Bit 3 (BP1)
Block Write Protect Bit 1
Bit 7
(WPBEN)
Write Protect Mode Enable Bit
Bits 4-6 are 0s when the device is not in an internal
write cycle; bits 0-7 are 1s during an internal write
cycle.
Write Sequence (WRITE)
Two separate instructions must be
executed in order to write to the
SA25C512. The device must first be write
enabled via the WREN instruction, and
then a WRITE instruction may be
executed. The address of the memory
locations to be written must be outside the
protected address field location selected by
the Block Write Protection level. During an
internal write cycle, all commands are
ignored except the RDSR instruction.
SA25C512 Data Sheet
SAIFUN
12
A WRITE instruction requires the following
sequence:
1. After the CSb line is pulled low to select
the device, the WRITE opcode is
transmitted via the SI line, followed by
the byte address and the data (D7-D0)
to be written.
2. Programming starts after the CSb pin is
brought high. The CSb pin's low-to-high
transition must occur during the SCK
low time, immediately after clock in the
D0 (LSB) data bit.
The SA25C512 is capable of up to a
128-byte (from 1 to 128 bytes) PAGE write
operation. After each byte is received, the
eight low-order address bits are internally
incremented by one. If more than 128
bytes of data are transmitted, the address
counter rolls over and the previously
written data is overwritten. The SA25C512
is automatically returned to the write
disable state at the completion of a write
cycle.
NOTE:
If the device is not write enabled, the
device ignores the WRITE instruction
and returns to the standby state when
CSb is brought high. A new CSb falling
edge is required to re-initiate the serial
communication.