NRF401 Datasheet, PDF (12/18 Pages) List of Unclassifed Manufacturers – 433MHz Single Chip RF Transceiver

PRODUCT SPECIFICATION
nRF401 Single Chip RF Transceiver
large surface mount capacitor (e.g. 2.2 µF ceramic) in parallel with the smaller value
capacitors. The nRF401 supply voltage should be filtered and routed separately from
the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD
connections and VDD bypass capacitors must be connected as close as possible to the
nRF401 IC. For a PCB with a topside RF ground plane, the VSS pins should be
connected directly to the ground plane. For a PCB with a bottom ground plane, the
best technique is to have via holes in or close to the VSS pads.
Full swing digital data or control signals should not be routed close to the PLL loop
filter components or the external VCO inductor.
The VCO inductor placement is important. The optimum placement of the VCO
inductor gives a PLL loop filter voltage of 1.1 ±0.2 V, which can be measured at
FILT1 (pin4). For a 0603 size inductor the length between the centre of the
VCO1/VCO2 pad and the centre of the inductor pad should be 5.4 mm, see Figure 13
(c) (layout, top view), for a 2 layer, 1.6 mm thick FR4 PCB.
PCB layout example
Figure 13 shows a PCB layout example for the application schematic in Figure 12.
A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a continuous
ground plane on the bottom layer. Additionally, there are ground areas on the
component side of the board to ensure sufficient grounding of critical components. A
large number of via holes connect the top layer ground areas to the bottom layer
ground plane. There is no ground plane beneath the antenna.
For more layout information, please refer to application note nAN400-05,
“nRF401 RF and antenna layout.
Nordic VLSI ASA -
Revision: 1.5
Vestre Rosten 81, N-7075 Tiller, Norway -
Page 12 of 18
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May 2000