NRF401 Datasheet, PDF (11/18 Pages) List of Unclassifed Manufacturers – 433MHz Single Chip RF Transceiver

PRODUCT SPECIFICATION
nRF401 Single Chip RF Transceiver
TXEN
0
0
1
1
X
Input
CS
0
1
0
1
X
PWR_UP
1
1
1
1
0
Response
Channel #
Mode
1
RX
2
RX
1
TX
2
TX
--
Standby
Table 8. Required setting for standby and channel selection in RX and TX.
D_IN (data input) and D_OUT (data output)
The DIN pin is the input to the digital modulator of the transmitter. The input signal
to this pin should be standard CMOS logic level at data rates up to 20 kbit/s. No
coding of data is required.
DIN = “1” → f = f₀ + ∆f
DIN = “0” → f = f₀ - ∆f
The demodulated digital output data appear at the D_OUT pin at standard CMOS logic
levels.
f₀ + ∆f → DOUT=“1”,
f₀ - ∆f → DOUT=“0”.
Power up
PWR_UP is a digital input for selection of normal operating mode or standby mode.
PWR_UP = “1” selects normal operating mode.
PWR_UP = “0” selects standby mode.
Frequency difference between transmitter and receiver
For optimum performance, the total frequency difference between transmitter and
receiver should not exceed 70 ppm (30 kHz). This yields a crystal stability
requirement of ±35 ppm for the transmitter and receiver. Frequency difference
exceeding this will result in a -12dB/octave drop in receiver sensitivity. The
functional frequency window of the transmission link is typically 450 ppm (200 kHz).
Example: A crystal with ±20 ppm frequency tolerance and ±25 ppm frequency
stability over the operating temperature has a worst case frequency difference of ±45
ppm. If the transmitter and receiver operate in different temperature environments, the
resulting worst-case frequency difference may be as high as 90 ppm. Resulting drop
in sensitivity due to the extra 20 ppm, is then approx. 5dB.
PCB layout and decoupling guidelines
A well-designed PCB is necessary to achieve good RF performance. A PCB with a
minimum of two layers including a ground plane is recommended for optimum
performance.
The nRF401 DC supply voltage should be decoupled as close as possible to the VDD
pins with high performance RF capacitors, see Table 9. It is preferable to mount a
Nordic VLSI ASA -
Revision: 1.5
Vestre Rosten 81, N-7075 Tiller, Norway -
Page 11 of 18
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May 2000