HPL5331 Datasheet, PDF (12/20 Pages) List of Unclassifed Manufacturers – 3A Bus Termination Regulator

HPL5331
A capacitor of 1µF (ceramic chip capacitor) or greater
(aluminum electrolytic capacitor) is recommended to
connect near VCNTL pin. For VIN pin, an aluminum
electrolytic capacitor (>50µF) is recommended. It is
not necessary to use low-ESR capacitors.
Layout and Thermal Consideration
The input capacitors for VIN and VCNTL pins are
normally placed near each pin for good
performances. Ceramic decoupling capacitors at
output must be placed as close to the load to reduce
the parasitic inductors of traces. It is also recom-
mended that the HPL5331 and output capacitors are
placed near the load for good load regulation and
load transient response. The negative pins of the in-
put and output capacitors and the GND pin of the
HPL5331 should connect to analog ground plane of
the load.
See figure 1. The SOP-8-P utilizes a bottom thermal
pad to minimize the thermal resistance of the package,
making the package suitable for high current
applications. The thermal pad is soldered to the top
ground pad and is connected to the internal or bot-
tom ground plane by several vias. The printed circuit
board (PCB) forms a heat sink and dissipates most
of the heat into ambient air. The vias are recom-
mended to have proper size to retain solder, helping
heat conduction.
Thermal resistance consists of two main elements,
θJC (junction-to-case thermal resistance) and θCA (case-
to-ambient thermal resistance). θJC is specified from
the IC junction to the bottom of the thermal pad di-
rectly below the die. θCA is the resistance from the
bottom of thermal pad to the ambient air and it in-
cludes θCS (case-to-sink thermal resistance) and θSA
(sink-to-ambient thermal resistance). The specified
path for heat flow is the lowest resistance path and it
dissipates majority of the heat to the ambient air.
Typically, θCA is the dominant thermal resistance.
Therefore, enlarging the internal or bottom ground
plane reduces the resistance θCA . The relationship
between power dissipation and temperatures is the
following equation :
PD = (TJ - TA) / ≤ θJA
where,
PD : Power dissipation
TJ : Junction Temperature
TA : Ambient Temperature
θJA : Junction-to-Ambient Thermal Resis-
tance
102 mil
118 mil
SOP-8-P
T herm al
Die
pad
Top
ground
pad
Ambient
Air
Vias
Internal Printed
ground circuit
plane board
Figure 1 Package Top and side view
Figure 2 shows a board layout using the SOP-8-P
package. The demo board is made of FR-4 material
and is a two-layer PCB. The size and thickness are
65mm* 65mm and 1.6mm. An area of 140mil*105mil
on the top layer is use as a thermal pad for the HPL5331
and this is connected to the bottom layer by vias. The
bottom layer using 2 oz. copper acts as the ground
plane for the system. The PCB and all components on
the board form a heat sink. The θJA of the HPL5331
(SOP-8-P) mounted on this demo board is about 37^oC/
W in free air. Assuming the TA=25^oC and the maxi-
mum TJ=150^oC (typical thermal limit temperature), the
maximum power dissipation is calculated as :
 Copyright HIPAC Semiconductor, Inc.
12
Rev. A.8 - Oct., 2003
www.hipacsemi.com