BT829A Datasheet, PDF (119/136 Pages) List of Unclassifed Manufacturers – VideoStream DECODER

Bt829A/827A
VideoStream II Decoders
CONTROL REGISTER DEFINITIONS
0x1B — Video Timing Control (VTC)
0x1B — Video Timing Control (VTC)
This register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. VFILT(0) is the
least significant bit. An asterisk indicates the default option.
7
6
5
4
3
2
1
0
HSFMT
0
ACTFMT
0
CLKGATE
0
VBIEN
0
VBIFMT
0
VALIDFMT
0
VFILT
0
0
HSFMT
This bit selects between a single-pixel-wide HRESET and the standard
64-clock-wide HRESET.
0* = HRESET is 64 CLKx1 cycles wide
1 = HRESET is 1 pixel wide
ACTFMT
This bit selects whether composite ACTIVE (HACTIVE and VACTIVE) or HAC-
TIVE only is output on the ACTIVE pin.
0* = ACTIVE is composite active
1 = ACTIVE is horizontal active
CLKGATE
This bit selects the signals that are gated with CLK to create QCLK. If logical zero
is selected, the ACTIVE pin (composite ACTIVE or HACTIVE) is used in gating
CLK.
0* = CLKx1 and CLKx2 are gated with DVALID and ACTIVE to
create QCLK.
1 = CLKx1 and CLKx2 are gated with DVALID to create QCLK.
VBIEN
This bit enables VBI data to be captured.
0* = Do not capture VBI
1 = Capture VBI
VBIFMT
This bit determines the byte ordering for VBI data.
0* = Pixel N on the VD[15:8] data bus, pixel N+1 on the VD[7:0] data
bus.
1 = Pixel N+1 on the VD[15:8] data bus, Pixel N on the VD[7:0] data
bus (Pixel N refers to the 1st, 3rd, 5th..., while pixel N+1 refers to
the 2nd, 4th, 6th in a horizontal line of video.)
L829A_B
109