CM6900 Datasheet, PDF (11/19 Pages) List of Unclassifed Manufacturers – PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP

CM6900
PFC/PWM COMBO w/ INRUSH CURRENT CONTROL & SEPARATED PFCOVP
Figure 1. PFC Section Block Diagram
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the types
of compensation networks most commonly used for the
voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to VREF to produce a soft-start characteristic on the
PFC: as the reference voltage comes up from zero volts, it
creates a differentiated voltage on IEAO which prevents the
PFC from immediately demanding a full duty cycle on its
boost converter.
PFC Voltage Loop:
There are two major concerns when compensating the
voltage loop error amplifier, VEAO; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest anticipated
international power frequency). The gain vs. input voltage
of the CM6900’s voltage error amplifier, VEAO has a
specially shaped non-linearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line or
load conditions will cause the input to the voltage error
amplifier (VFB) to deviate from its 2.5V (nominal) value. If
this happens, the transconductance of the voltage error
amplifier will increase significantly, as shown in the Typical
Performance Characteristics. This raises the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristics.
The Voltage Loop Gain (S)
= ^∆VOUT * ^∆VFB * ^∆VEAO
∆VEAO ∆VOUT ∆VFB
≈
PIN * 2.5V
V2
OUTDC
*
∆VEAO
*
S
*
CDC
* GMV * ZCV
ZCV: Compensation Net Work for the Voltage Loop
GMv: Transconductance of VEAO
PIN: Average PFC Input Power
VOUTDC: PFC Boost Output Voltage; typical designed value is
380V.
CDC: PFC Boost Output Capacitor
PFC Current Loop:
The current amplifier, IEAO compensation is similar to that of
the voltage error amplifier, VEAO with exception of the choice
of crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage loop.
It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.
The Current Loop Gain (S)
= ^{∆VISENSE} * ^∆DOFF * ^∆IEAO
∆DOFF ∆IEAO ∆ISENSE
≈ ^{VOUTDC * RS} * GMI * ZCI
S * L * 2.5V
2003/04/23 Preliminary Rev. 1.2
Champion Microelectronic Corporation
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