GS7000 Datasheet, PDF (10/14 Pages) List of Unclassifed Manufacturers – Serial Digital Video Transceiver

SMPTE
C₁ C₂
D_{IN (0,9)}
10
P to S
PCLK_OUT
H
SCRAMBLER
NRZI
ENCODER
f/10
PLL
MUX
SIGNAL
LOCK
DETECT
SDO
SDO
LOCK
CD
PCLK_IN
D_OUT(0,9)
S to P
TRS
DETECTOR
10
NRZI
SDI
DESCRAMBLER
DECODER
SLICER
EQUALIZER
SDI
SMPTE
Rx/Tx
EQ
Fig. 19 Functional Block Diagram (Transmitter Mode)
DIAGRAMS
The figure below describes the timing relationship between the outputs of the GS7000 when operating in receiver mode.
...
PCLK_OUT
XXX XXX 3FF 000 000 XXX XXX XXX XXX XXX ^... XXX XXX 3FF 000 000 XXX XXX XXX
SAV ID
EAV ID
D_OUT(n)
...
H
Fig. 20 Timing Diagram For Parallel Outputs, PCLK_OUT and H
The figure below describes the relationship between the output parallel clock and the output parallel data. The output
parallel clock rising edge is centered on the output data within ±5 ns.
WORD CENTER
5 ns
5 ns
D_OUT(n)
522 - 06 - 02
PCLK_OUT
Fig. 21 Receiver Parallel Clock Alignment
10