UL631H256 Datasheet, PDF (1/12 Pages) List of Unclassifed Manufacturers – Low Voltage SoftStore 32K x 8 nvSRAM

UL631H256
Low Voltage SoftStore 32K x 8 nvSRAM
Features
Description
S High-p erformance CMOS non-
volatile static RAM 32768 x 8 bits
S 35 and 45 ns Access Times
S 15 and 20 ns Output Enable
Access Times
S Software STORE Initiation
S Automatic STORE Timing
S 10⁶ STORE cycles to EEPROM
S 100 years data retention in
EEPROM
S Automatic RECALL on Power Up
S Software RECALL Initiation
S Unlimited RECALL cycles from
EEPROM
S Unlimited Read and Write to
SRAM
S Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
S Operating temperature range:
0 to 70 °C
-40 to 85 °C
S QS 9000 Quality Standard
S RoHS compliance and Pb- free
S ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
S Package: SOP28 (330 mil)
The UL631H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The UL631H256 is a fast static
RAM (35 and 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The UL631H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The UL631H256 is pin compatible
with standard SRAMs.
Pin Configuration
Pin Description
A14 1
28 VCC
A12 2
27 W
A7 3
26 A13
A6 4
25 A8
A5 5
24 A9
A4 6
23 A11
A3 7 _SOP 22 G
A2 8
21 A10
A1 9
20 E
A0 10
19 DQ7
DQ0 11
18 DQ6
DQ1 12
17 DQ5
DQ2 13
16 DQ4
VSS 14
15 DQ3
Top View
G
A11
A9
A8
A13
W
n. c.
VCC
n. c.
A14
A12
A7
A6
A5
A4
A3
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 _TSOP 25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
n.c.
Top View
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
April 7, 2005
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