IP100ALF Datasheet, PDF (1/97 Pages) List of Unclassifed Manufacturers – Integrated 10/100 Ethernet MAC + PHY

IP100A LF
Preliminary Data Sheet
Integrated 10/100 Ethernet MAC + PHY
Features
Single chip 10/100BASE, half or full duplex
Ethernet Media Access Controller
IEEE
802.3
compliant
100BASE-TX/100BASE-FX/10BASE-T
PCI Bus master scatter/gather DMA on any
byte boundary
Full operation with PCI Clock from 25 MHz to
33 MHz
PCI Revision 2.2 compliant
On-chip transmit and receive FIFO buffers
On-chip LED drivers
Power management capabilities for ACPI 1.0
compliant systems
WakeOnLAN support
Management statistics gathering
IP multicast receive and filter support using
64 bit hash table
Transmit polling
Auto pad insertion for short packets
Programmable minimum Inter Packet Gap
Supports auto MDI-MDIX function
Smart Cable Analyzer (SCA) Support
Capable of using 93C46 EEPROM
On-chip crystal oscillator
On-chip voltage regulator
2.5/3.3V CMOS with 5V tolerant I/O
0.25µm technology
128-pin PQFP
Support Lead Free package (Please refer to
the Order Information)
General Description
The IP100A LF is a single-chip, full duplex,
10/100Mbps Ethernet MAC + PHY incorporating a
32-bit PCI with bus master support. The IP100A
LF is designed for use in a variety of applications
including workstation NICs, PC motherboards,
and other systems utilizing a PCI bus that require
network connectivity to an Ethernet or Fast
Ethernet LAN.
The IP100A LF includes a PCI bus interface unit,
IEEE 802.3 compliant MAC, transmit and receive
FIFO buffers, IEEE 802.3 compliant 100BASE-TX,
10BASE-T, and 100BASE-FX PHY, serial
EEPROM interface and LED drivers.
The IP100A LF implements a rich set of control
and status registers. Accessible via the PCI
interface, these registers provide a host system
visibility into the features and operating state of
the IP100A LF. Network management statistics
are also recorded, and host access to registers of
the PHY device are facilitated through the IP100A
LF’s PCI interface.
The IP100A LF supports features for use in
“Green PCs” or systems where control over
system power consumption is desired. The
IP100A LF supports several power down states,
and the ability to issue a system “wake event” via
reception of unique, user defined Ethernet frames.
In addition, the IP100A LF can assert a wake
event in response to changes in the Ethernet link
status
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Copyright © 2004, IC Plus Corp.
March. 30, 2007
IP100A LF-DS-R17