M52S64322A Datasheet, PDF (9/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Mobile Synchronous DRAM

ESMT
M52S64322A
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores for selecting PASR; TCSR; DS. The extended mode register set must be done before any
active command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE
and high on BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended more register). The state of address pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in
the extended mode register. Refer to the table for specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as
long as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks
refreshed.
BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1000 0 0
DS
XX
PASR
Extended Mode Register Set
X = Don’t care
PASR
A2-A0
000
001
010
011
100
101
111
Self Refresh Coverage
4Bank
2 Bank (BankA& BankB) or
(BA1=0)
1 Bank (BankA) or
(BA0=BA1=0)
R
R
1/2 Bank (BankA) or
A10=BA0=BA1=0
R
Internal TCSR
A6-A5
00
DS
01
10
11
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
R
Remark R: Reserved
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
9/47