M52S64322A Datasheet, PDF (4/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Mobile Synchronous DRAM

ESMT
M52S64322A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T_A = 0 to 70 °C
Parameter
Symbol
Test Condition
Version
-7.5
-10
Operating Current
(One Bank Active)
ICC1
Precharge Standby
Current in power-down
mode
ICC2P
ICC2PS
Precharge Standby
Current in non
power-down mode
Active Standby Current
in power-down mode
ICC2N
ICC2NS
ICC3P
ICC3PS
Active Standby Current
in non power-down
mode
(One Bank Active)
ICC3N
ICC3NS
Operating Current
ICC4
(Burst Mode)
Refresh Current
ICC5
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
CKE ≤ VIL(max), tCC =15ns
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
CKE ≤ VIL(max), tCC =15ns
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 2clks
All other pins ≥ V_DD-0.2V or ≤ 0.2V
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
IOL= 0mA, Page Burst
All Band Activated, t_CCD = t_CCD (min)
tRFC ≥ tRFC(min)
70
60
1
0.5
10
7
5
5
50
40
110
80
115
110
TCSR range
70
Self Refresh Current
ICC6
CKE ≤ 0.2V
4 Banks
420
2 Bank
350
1 Bank
300
1/2 Bank
300
Deep Power Down
ICC7
CKE ≤ 0.2V
50
Current
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Unit Note
mA 1
mA
mA
mA
mA
mA
mA
mA
mA 1
mA 2
°C
uA
uA
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
4/47