M52D128168A-2E Datasheet, PDF (9/47 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
M52D128168A (2E)
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores for selecting PASR; DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE and
high on BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended
more register). The state of address pins
A0~An in the same cycle as CS , RAS , CAS , WE going low is written in the extended mode register. Refer to the table for
specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as
long as all banks are in the idle state.
Internal Temperature Compensated Self Refresh (TCSR)
Note:
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the device temperature.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
BA1 BA0
10
A11 ~ A8
0
A7 A6 A5 A4 A3 A2 A1 A0 Address bus
DS
TCSR
PASR
Extended Mode Register Set
PASR
A2-A0
000
001
010
011
100
101
110
111
Self Refresh Coverage
Full array
1/2 array (BA1=0)
1/4 array
(BA0=BA1=0)
Reserved
Reserved
1/8 array
Reserved
Reserved
Internal TCSR
Note: BA0 and A11~ A8 should stay “0” during EMRS cycle
A7-A5
Driver Strength
000
Full Strength
DS
001
010
1/2 Strength
1/4 Strength
011
1/8 Strength
100
3/4 Strength
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
9/47