M52D128168A-2E Datasheet, PDF (1/47 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
Mobile SDRAM
M52D128168A (2E)
2M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
FEATURES
y 1.8V power supply
y LVCMOS compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
y EMRS cycle with address
y All inputs are sampled at the positive going edge of the
system clock
y Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
ORDERING INFORMATION
Product ID
Max Freq. Package Comments
M52D128168A-5BG2E 200MHz 54 Ball FBGA
M52D128168A-6BG2E 166MHz 54 Ball FBGA
Pb-free
Pb-free
M52D128168A-7BG2E 143MHz 54 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152
words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
7
8
9
A
VSS DQ15 VSSQ
VDDQ DQ0 VDD
B
DQ14 DQ13 VDDQ
VSSQ DQ2 DQ1
C
DQ12 DQ11 VSSQ
VDDQ DQ4 DQ3
D
DQ10 DQ9 VDDQ
VSSQ DQ6 DQ5
E
DQ8
NC
VSS
VDD LDQM DQ7
F
UDQM CLK CKE
G
NC
A11
A9
CAS RAS
WE
BA0 BA1
CS
H
A8
A7
A6
J
VSS A5
A4
A0
A1
A10
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
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