M13S32321A Datasheet, PDF (8/49 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
PRECHARGE command
period
ACTIVE to READ with
AUTOPRECHARGE
command
ACTIVE bank A to ACTIVE
bank B command
Write recovery time
Write data in to READ
command delay
Col. Address to Col. Address
delay
Average periodic refresh
interval
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble
setup time
Load Mode Register /
Extended Mode register
cycle time
Exit self refresh to READ
command
Exit self refresh to
non-READ command
t_RP
t_RAP
t_RRD
t_WR
t_WTR
t_CCD
t_REFI
t_WPRE
t_WPST
t_RPRE
t_RPST
t_WPRES
t_MRD
t_XSRD
t_XSNR
Autoprecharge write
recovery+Precharge time
t_DAL
4
18
2
2
2
1
-
0.25
0.4
0.9
0.4
0
2
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
-
120K
-
-
-
-
7.8
-
0.6
1.1
0.6
-
-
-
-
4
18
2
2
2
1
-
0.25
0.4
0.9
0.4
0
2
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
M13S32321A
-
t_CK
120K
ns
-
t_CK
-
t_CK
-
t_CK
-
t_CK
7.8
us
-
t_CK
0.6
t_CK
1.1
t_CK
0.6
t_CK
-
ns
-
t_CK
-
t_CK
-
ns
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2006
Revision : 1.0
8/49