M13S32321A Datasheet, PDF (30/49 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
Current State _{CS RAS CAS WE}
Address
CS RAS CAS ^WE
H X X XX
L H H HX
L H H L BA
PRE-CHARGIN ^L
H
L
X BA, CA, A8
G
L
L
H
H BA, RA
L
L
H
L BA, A8
L
L
L
HX
L
L
L
L Op-Code Mode-Add
H X X XX
L H H HX
L H H L BA
ROW
L H L X BA, CA, A8
ACTIVATING _L
L
H
H BA, RA
L
L
H
L BA, A8
L
L
L
HX
L
L
L
L Op-Code Mode-Add
H X X XX
L H H HX
L H H L BA
L H L H BA, CA, A8
WRITE
RECOVERING
L
H
L
L BA, CA, A8
L
L
H
H BA, RA
L
L
H
L BA, A8
L
L
L
HX
L
L
L
L Op-Code Mode-Add
Command
DESEL
NOP
Burst Stop
READ/WRITE
Active
PRE / PREA
Refresh
MRS
DESEL
NOP
Burst Stop
READ / WRITE
Active
PRE / PREA
Refresh
MRS
DESEL
NOP
Burst Stop
READ
WRITE
Active
PRE / PREA
Refresh
MRS
Action
NOP (Idle after t_RP)
NOP (Idle after t_RP)
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
NOP*4 (Idle after t_RP)
ILLEGAL
ILLEGAL
NOP (ROW Active after t_RCD)
NOP (ROW Active after t_RCD)
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL*2
ILLEGAL*2
WRITE
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2006
Revision : 1.0
30/49