M53D128168A_1 Datasheet, PDF (7/46 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Mobile DDR SDRAM

ESMT
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-7.5
min
max
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE
command
t_HP
t_QH
t_QHS
t_RAS
t_CLmin or t_CHmin
t_HPmin-t_QHS
-
45
-
-
0.75
70K
Row Cycle Time
t_RC
67.5
-
AUTO REFRESH Row Cycle
Time
t_RFC
80
-
ACTIVE to READ,WRITE
delay
t_RCD
22.5
-
PRECHARGE command
period
t_RP
22.5
-
Minimum t_CKE High/Low time t_CKE
2
ACTIVE bank A to ACTIVE
bank B command
t_RRD
15
-
Write recovery time
t_WR
15
-
Write data in to READ
command delay
t_WTR
1
-
Col. Address to Col. Address
delay
t_CCD
1
-
Average periodic refresh
interval
t_REFI
-
15.6
Write preamble
t_WPRE
0.25
-
Write postamble
t_WPST
0.4
0.6
DQS read preamble
t_RPRE
0.9
1.1
DQS read postamble
t_RPST
0.4
0.6
Clock to DQS write preamble
setup time
t_WPRES
0
-
Load Mode Register /
Extended Mode register
t_MRD
2
-
cycle time
Exit self refresh to first valid
command
t_XSR
120
-
Exit power-down mode to
first valid command
t_XP
25
-
(t_WR/t_CK)
Autoprecharge write
recovery+Precharge time
t_DAL
+
-
(t_RP/t_CK)
M53D128168A
Operation Temperature Condition -40°C~85°C
-10
min
max
t_CLmin or t_CHmin
-
ns
t_HPmin-t_QHS
-
ns
-
1.0
ns
50
70K
ns
80
-
ns
90
-
ns
30
-
ns
30
-
ns
2
t_CK
15
-
ns
15
-
t_CK
1
-
t_CK
1
-
t_CK
-
0.25
0.4
0.9
0.4
0
15.6
us
-
t_CK
0.6
t_CK
1.1
t_CK
0.6
t_CK
-
ns
2
-
t_CK
120
25
(t_WR/t_CK)
+
(t_RP/t_CK)
-
ns
-
ns
-
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
7/46