M53D128168A_1 Datasheet, PDF (1/46 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Mobile DDR SDRAM

ESMT
Mobile DDR SDRAM
M53D128168A
Operation Temperature Condition -40°C~85°C
2M x 16 Bit x 4 Banks
Mobile DDR SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data
access per clock cycle
z Bi-directional data strobe (DQS)
z No DLL; CLK to DQS is not synchronized.
z Differential clock inputs (CLK and CLK )
z Quad bank operation
z CAS Latency : 2, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated Self
Refresh)
- DS (Driver Strength)
z All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
z Data mask (DM) for write masking only
z V_DD/V_DDQ = 1.7V ~ 1.9V
z Auto & Self refresh
z 15.6us refresh interval (64ms refresh period, 4K cycle)
z 1.8V LVCMOS-compatible inputs
z 60 ball BGA package
Ordering information :
Part NO.
MAX FREQ
M53D128168A -7.5BAIG
133MHz
M53D128168A -10BAIG
100MHz
VDD
1.8V
PACKAGE
8x13 mm
BGA
COMMENTS
Pb-free
Pb-free
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS
DM
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
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