M52S32162A_08 Datasheet, PDF (6/30 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16Bit x 2Banks Mobile Synchronous DRAM

ESMT
M52S32162A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in ^{CAS Latency =3}
Hi-Z
CAS Latency =2
Symbol
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
-6
Min
Max
6
1000
10
-
6
-
10
2.5
-
2
-
2
-
2
-
1.5
-
1
-
-
6
-
9
-7.5
Min
Max
7.5
1000
12
-
7
-
10
2
-
2.5
-
2.5
-
2
-
1.5
-
1
-
-
6
-
9
-10
Min
Max
9
1000
15
-
8
-
10
2
-
2.5
-
2.5
-
2
-
1.5
-
1
-
-
7
-
10
Unit Note
ns
1
ns
1
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
-
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Parameter
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
Output data hold time
Symbol
tSAC
tOH
-6
Min
Max
-
5.5
-
5.5
2
-
CAS Latency =3
-
CLK to output in
tSHZ
5.5
Hi-Z
CAS Latency =2
-
5.5
Note: 4. Special condition (Output Load ≤ 10 ohm+10 pF)
Unit Note
ns
4
ns
4
ns
4
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.4
6/30