M12L64322A Datasheet, PDF (6/44 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64322A
Parameter
Symbol
Col. address to col. address delay tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
Version
-6
-7
1
2
1
Unit
Note
CLK
3
ea
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
Parameter
Symbol
CLK cycle time
CAS latency = 3
tCC
CAS latency = 2
CLK to valid
output delay
CAS latency = 3
tSAC
CAS latency = 2
Output data
hold time
CAS latency = 3
tOH
CAS latency = 2
CLK high pulsh width
tCH
CLK low pulsh width
tCL
Input setup time
tSS
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output
in Hi-Z
CAS latency = 3
tSHZ
CAS latency = 2
-6
Min
Max
6
1000
8
5.5
6
2
2
2.5
2.5
1.5
1
1
5.5
6
-7
Unit Note
Min
Max
7
1000
ns
1
8.6
6
ns
1,2
6
2
ns
2
2
2.5
ns
3
2.5
ns
3
2
ns
3
1
ns
3
1
ns
2
6
ns
6
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
6/44