M12L64322A Datasheet, PDF (1/44 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
SDRAM
M12L64322A
512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6μs refresh interval
ORDERING INFORMATION
86 Pin TSOP (TypeII)
(400mil x 875mil)
Product No.
M12L64322A-6T
M12L64322A-7T
MAX FREQ.
166MHz
143MHz
PACKAGE
TSOPII
GENERAL DESCRIPTION
The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.
Synchronous design allows precise cycle control wi0th the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN ARRANGEMENT
Top View
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
NC 14
VDD 15
DQM0 16
WE 17
CAS 18
RAS 19
CS 20
N C 21
BA0 22
BA1 23
A10/AP 24
A0 25
A1 26
A2 27
D QM 2 28
VDD 29
NC 30
DQ16 31
VSSQ 32
DQ17 33
DQ18 34
VDDQ 35
DQ19 36
DQ20 37
VSSQ 38
DQ21 39
DQ22 40
VDDQ 41
DQ23 42
VDD 43
86 VSS
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VDDQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VDDQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 N C
56 DQ31
55
VDDQ
54 DQ30
53 DQ29
52
VSSQ
51 DQ28
50 DQ27
49
VDDQ
48 DQ26
47 DQ25
46
VSSQ
45 DQ24
44 VSS
86Pin TSOP(II)
(400mil x 875mil)
(0.5mm Pin pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
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