M12L32162A_09 Datasheet, PDF (6/29 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16Bit x 2Banks Synchronous DRAM

ESMT
M12L32162A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency =3
CLK cycle time
tCC
CAS Latency =2
CLK to valid
output delay
CAS Latency =3
tSAC
CAS Latency =2
Output data hold time
tOH
CLK high pulse width
tCH
CLK low pulse width
tCL
Input setup time
tSS
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output in ^{CAS Latency =3}
Hi-Z
CAS latency =2
tSHZ
-5.5
Min
Max
5.5
10
1000
6
6
2
2
2
2
2
0
6
6
-6
Min
Max
6
1000
10
5.5
5.5
2
2
2
2
2
0
5.5
5.5
-7
Min
Max
7
1000
10
6
6
2.5
2.5
2.5
2
2
0
6
6
Unit Note
ns
1
ns
1
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Parameter
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
Output data hold time
CLK to output in ^{CAS Latency =3}
Hi-Z
CAS Latency =2
Symbol
tSAC
tOH
tSHZ
-5.5
Min
Max
5.5
5.5
2
5.5
5.5
Note: 4. Special condition (Output Load ≤ 10 ohm+10 pF)
Unit Note
ns
4
ns
4
ns
4
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2
6/29