M12L64164A-2Y Datasheet, PDF (5/45 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
AC OPERATING TEST CONDITIONS (V_DD = 3.3V ± 0.3V)
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
VALUE
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870_Ω
3.3V
1200_Ω
VOH (DC) =2.4V , IOH = -2 mA
VOL (DC) =0.4V , IOL = 2 mA
50pF
Output
M12L64164A (2Y)
Z0 =50_Ω
UNIT
V
V
ns
V
Vtt = 1.4V
50_Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
VERSION
-5
-6
-7
Row active to row active delay
t_RRD(min)
10
12
14
RAS to CAS delay
t_RCD(min)
15
18
21
Row precharge time
t_RP(min)
15
18
21
Row active time
t_RAS(min)
38
40
42
t_RAS(max)
100
@ Operating
t_RC(min)
53
58
63
Row cycle time _{@ Auto refresh tRFC(min)}
55
60
70
Last data in to col. address delay
t_CDL(min)
1
Last data in to row precharge
t_RDL(min)
2
Last data in to burst stop
t_BDL(min)
1
Col. address to col. address delay t_CCD(min)
1
Refresh period (4,096 rows)
t_REF(max)
64
Number of valid
CAS latency = 3
2
Output data
CAS latency = 2
1
UNIT
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ms
ea
NOTE
1
1
1
1
1
1,5
2
2
2
3
6
4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t_RFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t_RFC(min)) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6 μ s.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1
5/45